REPORT: IP-ST Architecture Validation

Document Type: Technical Evidence / Vault Release Technology: Indexed Point-State Transfer (IP-ST)

This report summarises two independent simulation-based validation studies conducted to justify design choices for IP-ST prior to bench and road validation. Both tests quantify algorithmic and modelled network effects; actual end-to-end performance depends on hardware, OS scheduling, middleware configuration, and network equipment. Subsequent HIL/vehicle tests will provide final empirical confirmation.

Objective: Demonstrate that event-driven, asynchronous IP-ST factor-graph fusion (measurements anchored to their exact timestamps) preserves or improves accuracy while eliminating frame-gating latency versus a frame/batch pipeline — first under a moderate frame period, then under a coarse one.

Method: Synthetic 2D vehicle trajectory with accelerations, S-curve, and braking. Sensors: IMU (50–100 Hz), GNSS (~5–10 Hz with jitter/dropouts), LiDAR-like pose (~10–15 Hz with jitter). Estimator: factor-graph over time-knots with position/velocity states, smoothness prior (2nd diff), priors at start, and measurement factors at true timestamps (IP-ST) vs. frame-binned observations.

Scenario A — 100 ms frame period: • Accuracy: RMS ≈ 0.134 m for both IP-ST and frame/batch • Tail: p99 ≈ 0.244 m for both • Latency: IP-ST ≈ 0.1 ms vs. frame ≈ 100 ms (~T/2)

Scenario B — 400 ms frame period: • Accuracy: IP-ST RMS 0.148 m vs. frame 0.188 m • Tail: IP-ST p99 0.249 m vs. frame 0.315 m • Latency: IP-ST ≈ 0.1 ms vs. frame ≈ 200 ms (~T/2)

Interpretation: When frame period is modest (100 ms), IP-ST achieves the same accuracy while removing ~T/2 frame-wait latency. With coarse frames (400 ms) and fast dynamics, IP-ST improves both RMS and p99, because measurements are anchored to their real timestamps rather than binned to frame centres.

Algorithmic-latency figures exclude OS/middleware/network overhead; those are addressed in Test 2's virtual HIL and will be further validated with on-target ROS 2 tracing and TSN lab measurements. Sensors are synthetic; no real calibration bias or temperature drift is modelled.

Objective: Quantify end-to-end (E2E) latency distributions for four pipeline variants, separating the effect of the network (best-effort vs. TSN/gPTP) and the middleware (frame/batch vs. IP-ST). The goal is to predict median and tail benefits before physical HIL.

Method: 50,000 events, inter-arrival ~Exponential(1 ms) to mimic mixed sensor traffic.

Network models: • Best-effort Ethernet (BE): base 0.40 ms + lognormal queueing (background load → heavy tail) • TSN/gPTP: base 0.35 ms + bounded schedule wait U(0, 0.2 ms) + small jitter (models 802.1AS-synchronised, Qbv-scheduled stream)

Middleware: • Frame/Batch: coalescing period T=10 ms ⇒ average wait ≈ T/2 • IP-ST (event-driven): ε-dispatch ≈ 0.10 ms ± 0.03 ms (clipped ≥ 0.02 ms) • Processing: 0.80 ms ± 0.10 ms jitter (clipped ≥ 0.5 ms)

Scenarios tested: BE+Frame, BE+IPST, TSN+Frame, TSN+IPST.

IP-ST reduces median E2E latency ~4–5× vs. frame/batch under the same processing assumptions by removing the frame coalescing wait. TSN+IPST further tightens the tail (p95/p99) vs. BE+IPST thanks to bounded scheduling and a shared time base. BE+Frame and TSN+Frame remain dominated by the frame-wait (~T/2 on average).

Figure 1 — Virtual HIL: E2E Latency CDF (N=50,000) The CDF plot confirms that IP-ST variants (BE+IPST, TSN+IPST) reach CDF=1.0 before 3 ms, while Frame variants tail out to 12+ ms.

Figure 2 — Virtual HIL: Tail Distribution (log-scale) Log-scale tail density shows IP-ST variants concentrate energy below 2.5 ms. Frame variants exhibit a broad plateau extending to 12 ms, confirming the structural frame-wait penalty.

CDF of E2E latency (all four scenarios): https://media.base44.com/images/public/69a6abe94d6651bda636a1f2/eadcbb98b_IMG_4890.png

Tail density (log-scale): https://media.base44.com/images/public/69a6abe94d6651bda636a1f2/bc6056601_IMG_4891.png

vHIL models approximate TSN/gPTP bounded delay via a scheduled window and small jitter; exact values depend on the TSN profile and switch configuration. Middleware ε-dispatch is an algorithmic figure; real E2E includes executor scheduling, memory copies, cache effects, etc. (to be captured later with ROS 2 tracing on hardware).

1. IP-ST eliminates frame-gating latency: expect a structural ~T/2 reduction in algorithmic latency at equal or better accuracy, especially as frame periods grow or dynamics get sharper (Test 1).

2. TSN+IPST delivers the tightest tails: in vHIL, p95/p99 are lowest with TSN+IPST, consistent with bounded scheduling and a shared time base (Test 2).

3. Next steps: calibrate these predictions with on-target ROS 2/LTTng traces and a TSN lab setup, then repeat the same four-cell matrix in physical HIL.

The following artefacts are available to verified NDA signatories: • factor_graph_demo_summary.json — Factor-graph results, Scenario A (100 ms) • factor_graph_demo_summary_0p4s.json — Factor-graph results, Scenario B (400 ms) • fg_demo_traj.png — Estimated path vs. ground truth • fg_demo_error.png — Position error over time (cm) • vhil_latency_summary.json — vHIL latency summary (all four scenarios) • vhil_cdf.png — CDF of E2E latency • vhil_tail.png — Tail density (log-scale)

Both tests are simulation-based and intended to justify design choices prior to bench and road validation. Results quantify algorithmic and modelled network effects; actual E2E performance depends on hardware, OS scheduling, middleware configuration, and network equipment. Subsequent HIL/vehicle tests will provide the final empirical confirmation.